专利名称:Clock synchronous semiconductor memory
device
发明人:Takeshi Kajimoto申请号:US10173263申请日:20020618公开号:US06680866B2公开日:20040120
专利附图:
摘要:The position information indicating the position of a memory relative to acontroller is stored in a position information generating circuit, and the transfer timing ofwrite data transmitted from an input circuit to a write circuit and the activation timing of a
latch transfer instructing signal are adjusted according to this position information. Thus,the semiconductor memory device is provided that is capable of taking in and generatingthe internal write data reliably even when the flight time of a data bus becomessubstantially the same as the cycle time of a clock signal.
申请人:RENESAS TECHNOLOGY CORP.
代理机构:McDermott, Will & Emery
更多信息请下载全文后查看
因篇幅问题不能全部显示,请点此查看更多更全内容